1. Field of the Invention
The present invention relates to semiconductor circuit elements and, in particular, to use of a symmetric deep implant to provide a punch-through stopper that significantly reduces the possibility of parasitic device turn-on in DMOS power devices.
2. Discussion of the Related Art
Double-diffused Metal Oxide Semiconductor (DMOS) technology is widely used in power device applications.
Typically, in a vertical discrete DMOS device, the substrate forms the drain terminal with the MOSFET built into an epitaxial layer formed on the substrate. However, there are instances, particularly in embedded DMOS applications, where the "substrate" role is played by a buried layer in the integrated circuit substrate. In this case, the substrate can be either p or n type and still support an integrated DMOS device through the buried layer mechanism.
FIG. 1A shows a conventional DMOS device cross-section that includes an n+ buried layer 100, typically formed in a P- substrate (not shown), and an n- epitaxial layer 102 formed on the n+ buried layer 100. The n+/n- layers 100/102 serve as the drain of the vertical DMOS device, with the drain contact (not shown) typically made to the n-epitaxial layer 102. A double diffused p-type body region (or well) 104 serves as the device channel. A gate region that includes a patterned polysilicon gate electrode 106 and underlying gate oxide 107 that separates the polysilicon gate 106 from the channel region 104 form the channel modulating element in the MOSFET structure. The device source is provided by n+ diffusion regions 108. Source regions 108 are contacted by a metal interconnect structure 110 that is insulated from the polysilicon gate material 106 by an intermediate dielectric layer 112, typically borophosphosilicate glass (BPSG).
As discussed by Hu et al., "Second Breakdown of Vertical Power MOSFETs", IEEE, No. 8, August 1982, pp. 1287-1293, one of the problems associated with DMOS technology, when used to drive large inductive loads such as motors or long transmission lines, is that the transient waveforms generated during device operation can activate parasitic elements inherent in this topology and latch the device into destruction.
The FIG. 1A device cross section with key parasitic elements is shown in FIG. 1B; the circuit equivalent is shown in FIG. 1C.
The following could be outlined as a sequence of events leading to DMOS device failure: The device is turned on by a gate voltage which starts current flowing through the circuit. At some point, the device is switched off, thereby providing a high resistance path through the MOSFET. In an ideal case, all currents would cease. However, as mentioned above, in certain applications, a large inductance is associated with the load and its voltage follows the relationship -L di/dt. As a result of forcing a finite current through a virtually infinite resistance, a voltage exceeding the MOSFET breakdown value develops and the device begins to conduct large amounts of current through an avalanche breakdown mechanism. This current sets up internal biases within the device structure, with the result of activating the parasitic bipolar transistor. When this occurs, the MOSFET's maximum standoff voltage, commonly referred to as its breakdown voltage, is reduced by 20-30% and its current conduction becomes uncontrollable leading to thermal runaway and, ultimately, device destruction.
One way to avoid this problem is to "clamp" the inductor voltage externally with some type of rectifier device that turns on during avalanche mode, effectively shunting the inductor current.
Another way, in accordance with the present invention, is to address the problem at the device level. A device designed to avoid the destructive latch up condition described above is said to be "rugged."